The present invention relates to a method for forming a semiconductor device, and more particularly to a method for forming a semiconductor device including a buried gate.
Recently, many electronic appliances include semiconductor devices. Semiconductor devices include electronic elements, such as transistors, resistors, capacitors, and the like. These electronic elements are designed to perform functions of the electronic appliance and are integrated on a semiconductor substrate. For example, electronic appliances, such as computers, digital cameras, and the like, include semiconductor devices, such as memory chips for storage of information, processing chips for control of information, and the like. The memory chips and processing chips include electronic elements integrated on a semiconductor substrate.
The degree of integration of the semiconductor device has been increasing in order to satisfy consumer demands for superior performance and low prices. Such an increase in the integration degree of a semiconductor device entails a reduction in a design rule, causing patterns of a semiconductor device to be increasingly reduced. Although an entire chip area is increased in proportion to an increase in a memory capacity as a semiconductor device is becoming super miniaturized and highly integrated, a cell area where patterns of a semiconductor device are actually formed is decreased. Accordingly, since a greater number of patterns need to be formed in a limited cell area in order to achieve a desired memory capacity, there is a need for formation of microscopic patterns having a reduced critical dimension.
Nowadays, various methods for forming microscopic patterns have been developed, including, a method using a phase shift mask as a photo mask, a Contrast Enhancement Layer (CEL) method in which a separate thin film capable of enhancing image contrast is formed on a wafer, and a Tri Layer Resist (TLR) method in which an intermediate layer, such as, a Spin On Glass (SOG) film, is interposed between two photoresist films.
Meanwhile, a contact for connecting upper and lower conductive lines to each other is significantly affected by a design rule, as compared to line and space patterns. In more detail, an increase in the integration degree of a semiconductor device causes a reduction in a size of a contact and space between the contact and the neighboring conductive line. This causes an increase in an aspect ratio of the contact, that is, a ratio of a diameter to a depth of the contact. Therefore, a contact forming process holds an important position in a method for forming a highly integrated semiconductor device. Accordingly, in a highly integrated semiconductor device having multilayered conductive lines, a contact forming process may require a precise and strict mask alignment, entailing a reduction in process margin. This may cause a difficulty in manufacturing the semiconductor device with this lowered process margin.
In particular, a Self Align Contact (SAC) fail occurs between a landing plug and a gate or between a landing plug and a recess gate in a landing plug process, resulting in a reduced production yield. Therefore, there is proposed an improved technology for changing the gate or the recess gate structure to a buried gate structure to prevent the SAC fail from being generated between the recess or the recess gate structure and the landing plug.
However, the buried gate structure also has a disadvantage in that it causes the SAC fail between a storage electrode contact and a bit line, or the storage electrode contact is not connected to an active region.